The present invention relates to integrated circuits, more particularly, to edge seals for chips.
Edge seals for chips are generally used as mechanical and electrical barriers to contamination introduced in the chip sawing process.
FIG. 1 shows a semiconductor wafer 300 with a plurality of semiconductor chips 200 arranged in an array. Each semiconductor chip 200 contains circuitry to perform a specific function and has an edge seal 100 disposed along the edge thereof to prevent contamination by moisture and metal particles. Scribe lines 302 are arranged between semiconductor chips 200 where a saw can pass when separating the semiconductor chip.
FIG. 2 is a top view of semiconductor chip 200 comprising the edge seal 100 and FIG. 3 is a cross sectional view taken along line A–A′ of showing a dielectric layer IL on a semiconductor wafer 1 with a plurality of tungsten plugs 2 and metal lines 3, 5, 7, 9 of copper in the dielectric layer IL. Metal lines 3, 5, 7, and 9 are approximately parallel. A plurality of metal walls 4 are disposed between metal lines 3 and 5 comprising a plurality of trenches filled with a copper layer.
A plurality of metal walls 6 are disposed between the metal lines 5 and 7 with a plurality of metal walls 8 between metal lines 7 and 9. Metal walls 4, 6 on adjacent metal lines are staggered in the dielectric layer IL. Metal walls 6, 8 on the adjacent metal lines are also staggered and disposed in the dielectric layer IL.
Distance d1 between the metal wall 4 and the edges of metal lines 3 or 5 is large enough that delimitation P may occur at the dielectric layer IL at the edges of the metal lines 3 or 5 by thermal stress during packaging or test process.